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CGO 2004: San Jose, CA, USA

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2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA. IEEE Computer Society 2004, ISBN 0-7695-2102-9

Optimizing Memory Performance

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Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney:
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. 15-26
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Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen:
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. 27-38
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Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry:
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads. 39-52

New Frameworks

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Michael Dupré, Nathalie Drach, Olivier Temam:
VHC: Quickly Building an Optimizer for Complex Embedded Architectures. 53-64
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Sungdo Moon, Xinliang D. Li, Robert Hundt, Dhruva R. Chakrabarti, Luis A. Lozano, Uma Srinivasan, Shin-Ming Liu:
SYZYGY - A Framework for Scalable Cross-Module IPO. 65-74
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Chris Lattner, Vikram S. Adve:
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. 75-88

More Memory Performance

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Kim M. Hazelwood, James E. Smith:
Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems. 89-99
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  - conf/cgo/Adl-TabatabaiBCEFLMS04
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Ali-Reza Adl-Tabatabai, Jay Bharadwaj, Michal Cierniak, Marsha Eng, Jesse Fang, Brian T. Lewis, Brian R. Murphy, James M. Stichnoth:
Improving 64-Bit Java IPF Performance by Compressing Heap References. 100-110
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Xiaoming Li, María Jesús Garzarán, David A. Padua:
A Dynamically Tuned Sorting Library. 111-124

Optimizing for Energy Efficienc

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Ramon Canal, Antonio González, James E. Smith:
Software-Controlled Operand-Gating. 125-136
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Yoav Almog, Roni Rosner, Naftali Schwartz, Ari Schmorak:
Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture. 137-150

Loop Scheduling

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Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson:
Probabilistic Predicate-Aware Modulo Scheduling. 151-162
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Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao:
Single-Dimension Software Pipelining for Multi-Dimensional Loops. 163-174
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Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao:
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. 175-188

Instruction Scheduling

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Sebastian Winkel:
Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling. 189-200
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Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke:
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. 201-212
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Shiliang Hu, James E. Smith:
Using Dynamic Binary Translation to Fuse Dependent Instructions. 213-226

Code Profiling

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Youfeng Wu, Maurício Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang:
The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators. 227-238
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Rahul Joshi, Michael D. Bond, Craig B. Zilles:
Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems. 239-250
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Sriraman Tallam, Xiangyu Zhang, Rajiv Gupta:
Extending Path Profiling across Loop Backedges and Procedure Boundaries. 251-264

Compile-time Optimization

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Fabrice Rastello, François de Ferrière, Christophe Guillon:
Optimizing Translation Out of SSA Using Renaming Constraints. 265-278
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Yonghua Ding, Zhiyuan Li:
A Compiler Scheme for Reusing Intermediate Computation Results. 279-290

Memory Profiling and Data Layout

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Byoungro So, Mary W. Hall, Heidi E. Ziegler:
Custom Data Layout for Memory Parallelism. 291-302
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Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong:
Static Identification of Delinquent Loads. 303-314
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Qiang Wu, Artem Pyatakov, Alexey Spiridonov, Easwaran Raman, Douglas W. Clark, David I. August:
Exposing Memory Access Regularities Using Object-Relative Memory Profiling. 315-324

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