IEEE Transactions on Computers, Volume 42

Volume 42, Number 1, January 1993

Cache Memory

• 
  Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan:
  Modeling Live and Dead Lines in Cache Memory Systems. 1-14

Communication Protocols

• 
  Huai-An Lin, Chao-Li Tarng:
  An Inproved Method for Constructing Multiphase Communications Protocols. 15-26

Hypercube Fault Tolerance

• 
  Shahram Latifi:
  Combinatorial Analysis of the Fault-Diameter of the n-cube. 27-33

Interleaved Memories

• 
  Gurindar S. Sohi:
  High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. 34-44

Microcode Design

• 
  Christos A. Papachristou, Venkata R. Immaneni:
  Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing. 45-61

Multicomputer Dependability

• 
  Dong Tang, Ravishankar K. Iyer:
  Dependability Measurement and Modeling of a Multicomputer System. 62-75

Parallel Processor Architecture

• 
  Fernand Boéri, Michel Auguin:
  OPSILA: A Vector and Parallel Processor. 76-82

Server Policies

• 
  Alexander Thomasian, Victor F. Nicola:
  Performance Evaluation of a Threshold Policy for Scheduling Readers and Writers. 83-98

Correspondence

• 
  Yu Hen Hu, S. Naganathan:
  An Angle Recoding Method for CORDIC Algorithm Implementation. 99-102
• 
  David M. Mandelbaum:
  Some Results on a SRT Type Division Scheme. 102-106
• 
  Tai-Haur Kuo, Hung Chang Lin, Robert C. Potter, Dave Schupe:
  Multiple-Valued Counter. 106-109
• 
  T. Aaron Gulliver, Vijay K. Bhargava:
  A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors. 109-112
• 
  Andrew Spray, Simon Jones:
  Performance Tradeoffs in Rings of Data-Driven Elements. 113-118
• 
  Christophe Mazenc, Xavier Merrheim, Jean-Michel Muller:
  Computing Functions cos^{-1} and sin^{-1} Using Cordic. 118-122
• 
  Hwa C. Torng, Martin Day:
  Interrupt Handling for Out-of-Order Execution Processors. 122-127

Volume 42, Number 2, February 1993

• 
  Sreejit Chakravarty:
  A Characterization of Binary Decision Diagrams. 129-137
• 
  Imrich Chlamtac, Aura Ganz, Martin G. Kienzle:
  An HIPPI Interconnection System. 138-150
• 
  Biswanath Mukherjee, Subrata Banerjee:
  Alternative Strategies for Improving the Fairness in and an Analytical Model of the DQDB Network. 151-167
• 
  Jean Duprat, Jean-Michel Muller:
  The CORDIC Algorithm: New Results for Fast VLSI Implementation. 168-178
• 
  Niraj K. Jha:
  Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. 179-189
• 
  Andrew Choi, Manfred Ruschitzka:
  Managing Locality Sets: The Model and Fixed-Size Buffers. 190-204
• 
  Douglas M. Blough, Andrzej Pelc:
  Diagnosis and Repair in Multiprocessor Systems. 205-217
• 
  K. T. Sun, Hsin-Chia Fu:
  A Hybrid Neural Network Model for Solving Optimization Problems. 218-227
• 
  Tiko Kameda, Slawomir Pilarski, André Ivanov:
  Notes on Multiple Input Signature Analysis. 228-234

Correspondence

• 
  Raymond E. Fowkes:
  Hardware Efficient Algorithms for Trigonometric Functions. 235-239
• 
  Paolo Montuschi, Luigi Ciminiera:
  Reducing Iteration Time When Result Digit is Zero for Radix 2 SRT Division and Square Root with Redundant Remainders. 239-246
• 
  Nian-Feng Tzeng:
  A Cube-Connected Cycles Architecture with High Reliability and Improved Performance. 246-253
• 
  Anindo Bagchi, S. Louis Hakimi, Edward F. Schmeichel:
  Gossigping in a Distributed Network. 253-256

Volume 42, Number 3, March 1993

• 
  Andreas Farid Pour, Mark D. Hill:
  Performance Implications of Tolerating Cache Faults. 257-267
• 
  Antonio Lioy:
  On the Equivalence of Fanout-Point Faults. 268-271
• 
  Nageswara S. V. Rao:
  Expected-Value Analysis of Two Single Fault Diagnosis Algorithms. 272-280
• 
  Jordan L. Holt, Jenq-Neng Hwang:
  Finite Precision Error Analysis of Neural Network Hardware Implementations. 281-290
• 
  Ananth Sankar, Richard J. Mammone:
  Growing and Pruning Neural Tree Networks. 291-299
• 
  Martin Lades, Jan C. Vorbrüggen, Joachim M. Buhmann, Jörg Lange, Christoph von der Malsburg, Rolf P. Würtz, Wolfgang Konen:
  Distortion Invariant Object Recognition in the Dynamic Link Architecture. 300-311
• 
  Krishna R. Pattipati, Yong Li, Henk A. P. Blom:
  A Unified Framework for the Performability Evaluation of Fault-Tolerant Computer Systems. 312-326
• 
  Meera Balakrishnan, Cauligi S. Raghavendra:
  An Analysis of a Reliability Model for Repairable Fault-Tolerant Systems. 327-339
• 
  Aloke K. Das, Parimal Pal Chaudhuri:
  Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation. 340-352

Correspondence

• 
  Heinrich Braun, Frank Stephan:
  On Optimizing Diameter and Average Distance of Directed Interconnected Networks. 353-358
• 
  Appie van de Liefvoort, Narayan Subramanian:
  A New Approach for the Performance Analysis of a Single-Bus Multiprocessor System with General Service Times. 358-362
• 
  Antonio González, José M. Llabería:
  Reducing Branch Delay to Zero in Pipelined Processors. 363-371
• 
  George Miel:
  Constant Geometry Fast Fourier Transforms on Array Processors. 371-375
• 
  Colin D. Walter:
  Systolic Modular Multiplication. 376-378
• 
  Behrooz Parhami:
  On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems. 379-384

Volume 42, Number 4, April 1993

• 
  Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath:
  A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models. 385-395
• 
  Chris H. Perleberg, Alan Jay Smith:
  Branch Target Buffer Design and Optimization. 396-412
• 
  Marcel Lapointe, Huu Tuê Huynh, Paul Fortier:
  Systematic Design of Pipelined Recursive Filters. 413-426
• 
  Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza:
  A Systolic Redundant Residue Arithmetic Error Correction Circuit. 427-432
• 
  G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon:
  Multibit Correcting Data Interface for Fault-Tolerant Systems. 433-446
• 
  Nageswara S. V. Rao:
  Computational Complexity Issues in Operative Diagnosis of Graph-Based Systems. 447-457
• 
  Ashwini K. Nanda, Laxmi N. Bhuyan:
  Design and Analysis of Cache Coherent Multistage Interconnection Networks. 458-470
• 
  Ram Raghavan, John P. Hayes:
  Reducing Inerference Among Vector Accesses in Interleaved Memories. 471-483
• 
  Shambhu J. Upadhyaya, Hoang Pham:
  Analysis of Noncoherent Systems and an Architecture for the Computation of the System Reliability. 484-493

Correspondence

• 
  Benjamin Arazi:
  Architectures for Exponentiation Over GF(2^n) Adopted for Smartcard Application. 494-497
• 
  Nobuo Funabiki, Yoshiyasu Takefuji, Kuo Chun Lee:
  Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks. 497-501
• 
  Shyi-Chyi Cheng, Wen-Hsiang Tsai:
  A Neural Network Implementation of the Moment-Preserving Technique and Its Application to Thresholding. 501-507
• 
  Jacob van den Berg, Donald F. Towsley:
  Properties of the Miss Ratio for a 2-Level Storage Model with LRU or FIFO Replacement Strategy and Independent References. 508-512

Volume 42, Number 5, May 1993

• 
  Simon Y. Berkovich:
  An Overlaying Technique for Solving Linear Equations in Real-Time Computing. 513-517
• 
  Douglas M. Blough, Andrzej Pelc:
  A Clustered Failure Model for the Memory Array Reconfiguration Problem. 518-528
• 
  Jesse Zhixi Fang, Mi Lu:
  An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing. 529-546
• 
  Yuichi Saitoh, Hideki Imai:
  Some Codes for Correcting and Detecting Unidirectional Byte Errors. 547-552
• 
  Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae:
  Availability of k-Coterie. 553-558
• 
  Barry G. Douglass:
  Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties. 559-567
• 
  Daniel Brand, Tsutomu Sasao:
  Minimization of AND-EXOR Expressions Using Rewrite Rules. 568-576
• 
  Chunming Qiao, Rami G. Melhem:
  Time-Division Optical Communications in Multiprocessor Arrays. 577-590
• 
  Pablo P. Trabado, Antonio Lloris-Ruíz, Julio Ortega Lopera:
  Solution of Switching Equations Based on a Tabular Algebra. 591-596
• 
  Andrew Lim, Siu-Wing Cheng, Sartaj Sahni:
  Optimal Joining of Compacted Cells. 597-607

Correspondence

• 
  Giovanni Dimauro, Sebastiano Impedovo, Giuseppe Pirlo:
  A New Technique for Fast Number Comparison in the Residue Number System. 608-61
• 
  Ding-Zhu Du, Yuh-Dauh Lyuu, D. Frank Hsu:
  Line Digraph Iterations and Connectivity Analysis of de Bruijn and Kautz Graphs. 612-616
• 
  David T. Harper III, Yashodara Costa:
  Analytical Estimation of Vector Access Performance in Parallel Memory Architectures. 616-624
• 
  Seshu V. R. Madabhushi, S. Lakshmivarahan, Sudarshan K. Dhall:
  A Note on Orthogonal Graphs. 624-630
• 
  Daniel J. Rosenkrantz, S. S. Ravi:
  Improved Bounds for Algorithm-Based Fault Tolerance. 630-635
• 
  Tao Wang, Xinhua Zhuang, Xiaoliang Xing, Xipeng Xiao:
  A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories. 636-640

Volume 42, Number 6, June 1993

• 
  Janusz Rajski, Jerzy Tyszer:
  Accumulator-Based Compaction of Test Responses. 643-650
• 
  Edward K. Lee, Randy H. Katz:
  The Performance of Parity Placements in Disk Arrays. 651-664
• 
  Nabanita Das, Bhargab B. Bhattacharya, Jayasree Dattagupta:
  Isomorphism of Conflict Graphs in Multistage Interconnection Networks and Its Application to Optimal Routing. 665-677
• 
  Russ Miller, Viktor K. Prasanna, Dionisios I. Reisis, Quentin F. Stout:
  Parallel Computations on Reconfigurable Meshes. 678-692
• 
  Stephen E. Eldridge, Colin D. Walter:
  Hardware Implementation of Montgomery's Modular Multiplication Algorithm. 693-699
• 
  Stanislaw J. Piestrak:
  The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks. 700-712
• 
  Yung-Yuan Chen, Shambhu J. Upadhyaya:
  Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy. 713-723
• 
  Israel Koren, Zahava Koren, Charles H. Stapper:
  A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. 724-734

Correspondence

• 
  Reuven Cohen:
  One-Bit Delay in Ring Networks. 735-737
• 
  Ahmed E. Kamal, V. Carl Hamacher:
  Response to "One-Bit Delay in Ring Networks". 737-738
• 
  David Fernández-Baca, A. Medepalli:
  Parametric Module Allocation on Partial k-Trees. 738-742
• 
  Alireza Kavianpour, Nader Bagherzadeh:
  A Systematic Approch for Mapping Application Tasks in Hypercubes. 742-746
• 
  Hussein M. Alnuweiri:
  A New Class of Optimal Bounded-Degree VLSI Sorting Networks. 746-752
• 
  Richard Hughey:
  Concurrent Error Detection on Programmable Systolic Arrays. 752-756
• 
  Sidney W. Graham, Steven R. Seidel:
  The Cost of Broadcasting on Star Graphs and k-Ary Hypercubes. 756-759
• 
  Vitit Kantabutra:
  Designing Optimum One-Level Carry-Skip Adders. 759-764
• 
  Vijay Raghavan:
  On Asymmetric Invalidation with Partial Tests. 764-768

Volume 42, Number 7, July 1993

Cordic Arithmetic

• 
  Kishore Kota, Joseph R. Cavallaro:
  Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. 769-779

Error Detection

• 
  Ramesh K. Sitaraman, Niraj K. Jha:
  Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. 780-793

Fault-Tolerant Systems

• 
  Abhijit Chatterjee, Manuel A. d'Abreu:
  The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques. 794-808

Heterogeneous Distributed Systems

• 
  Kurt Geihs, Reinhard Heite, Ulf Hollberg:
  Protected Object References in Heterogeneous Distributed Systems. 809-816

Number Systems

• 
  Jean Duprat, Yvan Herreros, Sylvanus Kla:
  New Redundant Representations of Complex Numbers and Vectors. 817-824

Pipeline Processing

• 
  Stamatis Vassiliadis, James Phillips, Bart Blaner:
  Interlock Collapsing ALU's. 825-839

Residue Number Systems

• 
  Hari Krishna, Jenn-Dong Sun:
  On Theory and Fast Algorithms for Error Correction in Residue Number System Product Codes. 840-853

Systolic Arrays

• 
  Edwin Hsing-Mean Sha, Kenneth Steiglitz:
  Reconfigurability and Reliability of Systolic/Wavefront Arrays. 854-862

Vector Processing

• 
  Woei Lin:
  Manipulating General Vectors on Synchronous Binary N-Cube. 863-871

Yield Modeling

• 
  Charles H. Stapper:
  Improved Yield Models for Fault-Tolerant Memory Chips. 872-881

Correspondence

• 
  Sunggu Lee, Kang G. Shin:
  Optimal and Efficient Probabilistic Distributed Diagnosis Schemes. 882-886
• 
  Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan:
  Design of Pseudoexhaustive Testable PLA with Low Overhead. 887-891
• 
  Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao:
  Berger Check Prediction for Array Multipliers and Array Dividers. 892-896

Volume 42, Number 8, August 1993

Concurrent Testing

• 
  Julio Ortega Lopera, Alberto Prieto, Antonio Lloris-Ruíz, Francisco J. Pelayo:
  Generalized Hopfield Neural Network for Concurrent Testing. 898-912

Dependability Evaluation

• 
  Jean Arlat, Alain Costes, Yves Crouzet, Jean-Claude Laprie, David Powell:
  Fault Injection and Dependability Evaluation of Fault-Tolerant Systems. 913-923

Fault-Tolerance

• 
  Bapiraju Vinnakota, Niraj K. Jha:
  Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. 924-937

Interconnection Networks

• 
  Sandeep N. Bhatt, Geppino Pucci, Abhiram G. Ranade, Arnold L. Rosenberg:
  Scattering and Gathering Messages in Networks of Processors. 938-949

Multiple-Valued Logic

• 
  Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato:
  Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas. 950-961

Residue Number Systems

• 
  Giuseppe Alia, Enrico Martinelli:
  On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation. 962-967

Test-Pattern Generation

• 
  Julio Ortega Lopera, Antonio Lloris-Ruíz, Alberto Prieto, Francisco J. Pelayo:
  Test-Pattern Generation Based on Reed-Muller Coefficients. 968-980

Correspondence

• 
  Judy Stephens, Vijaj Raghavan:
  On Single-Fault Set Diagnosability in the PMC Model. 981-983
• 
  Anindya Das, Krishnaiyan Thulasiraman, Vinod K. Agarwal, K. B. Lakshmanan:
  Multiprocessor Fault Diagnosis Under Local Constraints. 984-988
• 
  Sung-Kwong Park, Jung H. Kim:
  Geometrical Learning Algorithm for Multilayer Neural Networks in a Binary Field. 988-992
• 
  Dinesh P. Mehta, Sartaj Sahni:
  A Data Structure for Circular String Analysis and Visualization. 992-997
• 
  John E. Sasinowski, Jay K. Strosnider:
  A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems. 997-1001
• 
  Khaled Day, Anand R. Tripathi:
  Embedding of Cycles in Arrangement Graphs. 1002-1006
• 
  Steven Arno, Ferrell S. Wheeler:
  Signed Digit Representations of Minimal Hamming Weight. 1007-1009
• 
  Hannes Brunner, Andreas Curiger, Max Hofstetter:
  On Computing Multiplicative Inverses in GF(2^m). 1010-1015
• 
  Sarit Mukherjee, Satish K. Tripathi, Dipak Ghosal:
  A Multiclass Priority-Based Slotted-Ring LAN and Its Analysis. 1015-1020
• 
  T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo:
  Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. 1020-1024

Volume 42, Number 9, September 1993

Asynchronous State Assignment

• 
  P. David Fisher, Sheng-Fu Wu:
  Race-Free State Assignment for Synthesizing Large-Scale Asynchronous Sequential Logic Circuits. 1025-1034

Built-In Test

• 
  Mark G. Karpovsky, Saeed M. Chaudhry:
  Design of Self-Diagnostic Boards by Multiple Signature Analysis. 1035-1044

Cache Design

• 
  William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu:
  The Effect of Code Expanding Optimizations on Instruction Cache Design. 1045-1057

Eigenvalue Computation

• 
  Jürgen Götze, Steffen Paul, Matthias Sauer:
  An Efficient Jacobi-like Algorithm for Parallel Eigenvalue Computation. 1058-1065

Fault Detection

• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Classification of Faults in Synchronous Sequential Circuits. 1066-1077

Fault-Tolerant Hypercubes

• 
  Jong Kim, Kang G. Shin:
  Deadlock-Free Fault-Tolerant Routing in Injured Hypercubes. 1078-1088

Fault-Tolerant Meshes

• 
  Jehoshua Bruck, Robert Cypher, Ching-Tien Ho:
  Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares. 1089-1104

Interconnection Networks

• 
  Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault:
  Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection. 1105-1120

Scan Testing

• 
  Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer:
  Optimal Configuring of Multiple Scan Chains. 1121-1131

Correspondence

• 
  William A. Porter, Xiaoyan Zheng:
  A Nonbinary Neural Network Design. 1132-1135
• 
  Yung-Yuan Chen, Shambhu J. Upadhyaya:
  Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. 1136-1141
• 
  Chin-Liang Wang, Jung-Lung Lin:
  A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m). 1141-1146
• 
  Kien A. Hua, Lishing Liu, Jih-Kwon Peir:
  Designing High-Performance Processors Using Real Address Prediction. 1146-1151
• 
  Masakatu Morii, Kazuhiko Iwasaki:
  A Note on Aliasing Probability for Multiple Input Signature Analyzer. 1152

Volume 42, Number 10, October 1993

Cache Design

• 
  Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu:
  A Quantitative Evaluation of Cache Types for High-Performance Computer Systems. 1154-1162

Carry-Select Adders

• 
  Akhilesh Tyagi:
  A Reduced-Area Scheme for Carry-Select Adders. 1163-1170

Computational Models

• 
  Sang-Hwa Chung, Dan I. Moldovan, Ronald F. DeMara:
  A Parallel Computational Model for Integrated Speech and Natural Language Understanding. 1171-1183

Failure Repair Models

• 
  Phillip F. Chimento Jr., Kishor S. Trivedi:
  The Completion Time of Programs on Processors Subject to Failure and Repair. 1184-1194

Fault Tolerance

• 
  Nitin H. Vaidya, Dhiraj K. Pradhan:
  Fault-Tolerant Design Strategies for High Reliability and Safety. 1195-1206
• 
  Charles J. Colbourn, John S. Devitt, Daryl D. Harms, Miro Kraetzl:
  Assessing Reliability of Multistage Interconnection Networks. 1207-1221

Neural Networks

• 
  Avijit Saha, Chuan-lin Wu, Dun-Sung Tang:
  Approximation, Dimension Reduction, and Nonconvex Optimization Using Linear Superpositions of Gaussians. 1222-1233

Nonrestoring Division

• 
  Eric M. Schwarz, Michael J. Flynn:
  Parallel High-Radix Nonrestoring Division. 1234-1246

Correspondence

• 
  Nian-Feng Tzeng, Po-Jen Chuang, Chwan-Hwa John Wu:
  Creating Disjoint Paths in Gamma Interconnection Networks. 1247-1252
• 
  Philip J. Bernhard:
  Bounds on the Performance of Message Routing Heuristics. 1253-1256
• 
  Thanos Stouraitis:
  Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors. 1257-1261
• 
  Sulaiman Al-Bassam, Bella Bose:
  Design of Efficient Error-Correcting Balanced Codes. 1261-1266
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. 1267-1271
• 
  Shirish Bhide, Nigel M. John, Mansur R. Kabuka:
  A Boolean Neural Network Approach for the Traveling Salesman Problem. 1271-1278
• 
  M. Anwarul Hasan, Muzhong Wang, Vijay K. Bhargava:
  A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields. 1278-1280

Volume 42, Number 11, November 1993

Array Configuration

• 
  Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath:
  Reconfiguring Processor Arrays Using Multiple-Track Models: The 3-Track-1-Spare-Approach. 1281-1293

Error-Correcting Codes

• 
  Mao Chao Lin:
  Constant Weight Codes for Correcting Symmetric Errors and Detecting Unidirectional Errors. 1294-1302

Fault Tolerance

• 
  Luiz A. Laranjeira, Miroslaw Malek, Roy M. Jenevein:
  Nest: A Nested-Predicate Scheme for Fault Tolerance. 1303-1324

Logic Minimization

• 
  Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  Two-Level Minimization of Multivalued Functions with Large Offsets. 1325-1342

Network Modeling

• 
  Giovanni Chiola, Claude Dutheillet, Giuliana Franceschinis, Serge Haddad:
  Stochastic Well-Formed Colored Nets and Symmetric Modeling Applications. 1343-1360

Sequential Testing

• 
  Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee:
  An Efficient Algorithm for Sequential Circuit Test Generation. 1361-1371

Signature Monitoring

• 
  Kent D. Wilken:
  An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring. 1372-1381

Wafer Packing

• 
  David Hung-Chang Du, Ichiang Lin, K. C. Chang:
  On Wafer-Packing Problems. 1382-1388

Correspondence

• 
  Vitit Kantabutra:
  Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders. 1389-1393
• 
  Jenn-Yang Tien, Ching-Tien Ho, Wei-Pang Yang:
  Broadcasting on Incomplete Hypercubes. 1393-1398
• 
  Nader Bagherzadeh, Nayla Nassif, Shahram Latifi:
  A Routing and Broadcasting Scheme on Faulty Star Graphs. 1398-1403
• 
  Jung Hwan Kim, Phill-Kyu Rhee:
  The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays. 1403-1408

Volume 42, Number 12, December 1993

Cache Design

• 
  Qing Yang:
  Introducing a New Cache Design into Vector Computers. 1411-1424

Database Management Systems

• 
  Kien A. Hua, Jeffrey X. W. Su:
  Dynamic Load Balancing in Very Large Shared-Nothing Hypercube Database Computers. 1425-1439

Dependability Evaluation

• 
  Victor F. Nicola, Marvin K. Nakayama, Philip Heidelberger, Ambuj Goyal:
  Fast Simulation of Highly Dependable Systems with General Failure and Repair Processes. 1440-1452

Dram Design

• 
  Pinaki Mazumder:
  Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit. 1453-1468

Interconnection Networks

• 
  Ching Yuh Jan, A. Yavuz Oruç:
  Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network. 1469-1479
• 
  Robert A. Rowley, Bella Bose:
  Fault-Tolerant Ring Embedding in de Bruijn Networks. 1480-1486

Synchronizer Reliability

• 
  Ahmed El-Amawy, Morteza Naraghi-Pour, Manju V. Hegde:
  Noise Modeling Effects in Redundant Synchronizers. 1487-1494

Correspondence

• 
  Vitit Kantabutra:
  A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. 1495-1499
• 
  Laura A. Sanchis:
  Multiple-Way Network Partitioning with Different Cost Functions. 1500-1504
• 
  Rolf Johansson:
  A Class of (12, 8) Codes for Correcting Single Errors and Detecting Double Errors within a Nibble. 1504-1506
• 
  Keumog Ahn, Sartaj Sahni:
  NP-Hard Module Rotation Problems. 1506-1510
• 
  Hong Hao, Edward J. McCluskey:
  Analysis of Gate Oxide Shorts in CMOS Circuits. 1510-1516
• 
  Janusz Rajski, Jerzy Tyszer:
  Recursive Pseudoexhaustive Test Pattern Generation. 1517-1521